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1 features ? 20ns read, 10ns write maximum access times ? functionally compatible with traditional 512k x 32 sram devices ? cmos compatible inputs and output levels, three-state bidirectional data bus - 3.3 volt i/o, 1.8 volt core ? radiation performance - total-dose: >100krad(si) - sel immune: 100mev-cm 2 /mg - seu error rate = 6.01x10 -16 errors bit/day assuming geosynchronous orbit, adam?s 90% worst environment, and 156khz default scrub rate (=99.4% sram availability) - neutron fluence: 3.0e14n/cm 2 - dose rate - upset tbd rad(si)/sec - latchup tbd rad(si)/sec ? packaging options: - 68-lead ceramic quad flatpack (6.898 grams) ? standard microcircuit drawing 5962-06261 - qml compliant part introduction the ut8er512k32 is a high-performance cmos static ram organized as 524,288 words by 32 bits. easy memory expansion is provided by active low and high chip enables (e1 , e2), an active low output enable (g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to the device is accomplishe d by driving chip enable one (e1 ) input low, chip enable tw o (e2) high and write enable (w ) input low. data on the 32 i/o pins (dq0 through dq31) is then written into the location specified on the address pins (a0 through a18). reading from the device is accomplished by taking chip enable one (e1 ) and output enable (g ) low while forcing write enable (w ) and chip enable two (e2) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the 32 input/output pins (dq0 through dq31) are placed in a high impedance state when th e device is deselected (e1 high or e2 low), the outputs are disabled (g high), or during a write operation (e1 low, e2 high and w low). ut8er512k32 master or slave options to reduce bit error rates caused by single event phenomenon in space, the ut8er512k32 employs an embedded edac (error detection and correction) with code engine with auto scrubbing. when a double bit error occurs in a word, the ut8er512k32 asserts an mbe output to the host. the ut8er512k32 is offered in two options: master or slave. the ut8er512k32m (master) is a full function device capable of autonomous edac scrubbing which can also be used to demand scrub cycles on the ut8er512k32s (slave) by connecting the scrub pins on each device. the ut8er512k32s (slave) only performs edac scrub cycles when its scrub pin is driven by an external controller. the scrub-on-demand feature allows multiple ut8er512k32s (slave) devices to be controlled by one ut8er512k32m (master) device. the scrub function is a no connect (nc) on the ut8er512k32s (slave), and is used by the ut8er512k32m (master) to generate wait states in the memory controller. the busy function is an output on the master device while on the sl ave device it is an input. standard products ut8er512k32 monolithic 16m radhard sram preliminary data sheet may 21, 2007 www.aeroflex.com/radhardsram
2 figure 1. ut8er512k32 sram block diagram memory array 512k x 32 pre-charge circuit column select row select a3 a4 a6 a7 a8 a9 a17 a18 data control i/o circuit a10 a11 a12 a13 a14 a15 dq(31) to dq(0) e1 w e2 g a2 a16 read/write circuit edac a5 a1 a0 busy, scrub mbe
3 note: pin 30 on the ut8er512k32s (slave) is a no connect (nc). pin descriptions device operation the ut8er512k32 has four control inputs called enable 1 (e1 ), enable 2 (e2), write enable (w ), and output enable (g ); 19 address inputs, a(18:0); and 32 bidirectional data lines, dq(31:0). e1 and e2 device enables control device selection, active, and standby modes. asserting e1 and e2 enables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. w controls read and write operatio ns. during a read cycle, g must be asserted to enable the outputs. table 1. sram device control operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. table 2. edac control pin operation truth table notes: 1. ?x? is defined as a ?don?t care? condition pins type description a(18:0) i address dq(31:0) bi data input/output e1 i enable (active low) e2 i enable (active high) w i write enable g i output enable v dd1 p power (1.8) v dd2 ppower (3.3v) v ss p ground mbe tto multiple bit error scrub i slave scrub input scrub o master scrub output busy nc slave no connect busy o master wait state control 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 top view dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 v ss dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 v ss a0 a1 a2 a3 a4 a5 a17 v ss a18 w a6 a7 a8 a9 a10 v dd1 v dd1 a11 a12 a13 a14 a15 a16 e1 g e2 v dd2 v ss scrub busy mbe v dd2 v ss dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 figure 2. 20ns sram pinout (68) 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 g w e2 e1 i/o mode mode xxxhdq(31:0) 3-state standby x x l x dq(31:0) 3-state standby l h h l dq(31:0) data out word read x l h l dq(31:0) data in word write h x x l dq(31:0) all 3-state 3-state mbe scrub busy i/o mode mode h h h read uncorrectable bit error l h h read valid data out xh h x device ready x h l x device ready / early scrub request coming x l x not accessible device busy
4 read cycle a combination of w and e2 greater than v ih (min) and e1 and g less than v il (max) defines a read cycle. read access time is measured from the latter of device enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 3a, is initiated by a change in address i nputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(31:0) after the specified t avqv is satisfied. outputs remain active throughout the entire cycle. as long as device enable and output enable are active, the minimum time between valid address changes is specifi ed by the read cycle time (t avav ). sram read cycle 2, the chip enable-controlled access in figure 3b, is initiated by the latter of either e1 and e2 going active while g remains asserted, w remains deasserted, and the addresses remain stable for the entire cycle. after the specified t etqv is satisfied, the 32-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(31:0). sram read cycle 3, the output enable-controlled access in figure 3c, is initiated by g going active while e1 and e2 are asserted, w is deasserted, and the addresses are stable. read access time is t glqv unless t avqv or t etqv (reference figure 3b) have not been satisfied. sram edac status indications during a read cycle, if mbe is low, the data is good. if mbe is high the data is corrupted. write cycle a combination of w and e1 less than v il (max) and e2 greater than v ih (min) defines a write cy cle. the state of g is a ?don?t care? for a write cycle. the out puts are placed in the high- impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable-controlled access in figure 4a, is defined by a write terminated by w going high, with e1 and e2 still active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e1 and e2. unless the outputs have been previously placed in the high-impedance state by g , the t wlqz before applying data to the 32 bidirectional pins dq(31:0) to avoid bus contention. write cycle 2, the chip enable -controlled access in figure 4b, is defined by a write terminated by the latter of e1 or e2 going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by either e1 or e2 going active. for the w initiated write, unless the outputs have been previous ly placed in the high-impedance state by g , the user must wait t wlqz before applying data to the thirty-two bidirectional pins dq(31:0) to avoid bus contention. memory scrubbing/cycle stealing the ut8er512k32 sram uses architectural improvements and embedded error detection and correction to maintain unsurpassed levels of seu protect ion. this is accomplished by what aeroflex refers to as cycle stealing. to minimize the system design impact for redu ced speed operation, the edge relationship between busy and scrub is programmable via the sequence described in figure 5a. the effective error rate will be flux dependent (rate at which radiation is applied) and not simply let dependent. as a result, some users may desire an increased scrub rate to lower the error rate at the sacrifice of reduced total throughput, while others may desire a lower scrub rate to increase the total throughput and accept a higher error rate in a low flux environment. this rate at which the sram controller will correct errors from the memory is user programmable. the required sequence is described in figure 5a. data is corrected not only durin g the internal scrub, but again during a user requeste d read cycle. the mbe signal is asserted once the data is valid (t avav ), if the data presented contains at least two errors and should be considered corrupt. (note: reading un-initialized memory locations may result in un- intended mbe assertions.) radiation hardness the ut8er512k32 sram incorporates special design, layout, and process features which allows operation in a limited radiation environment. table 3. radiation hardness design specifications 1 notes: 1. the sram is immune to latchup to particles >100mev-cm 2 /mg. 2. 90% worst case particle environmen t, geosynchronous orbit, 100 mils of aluminum. supply sequencing no supply voltage sequencing is required between v dd1 and v dd2 . total dose 100k rad(si) heavy ion error rate 2 tbd errors/bit-day
5 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limit s indicated in the operationa l sections of this specific ation is not recommended. exposure to absolu te maximum rating conditions for extended periods may af fect device reliability and performance. 2. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd1 dc supply voltage (core) -0.3 to 2.0v v dd2 dc supply voltage (i/o) -0.3 to 3.8v v i/o voltage on any pin -0.3 to 3.8v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.2w t j maximum junction temperature +150 c jc thermal resistance, junction-to-case 2 5 c/w i i dc input current 5 ma symbol parameter limits v dd1 dc supply voltage (core) 1.7 to 1.9v v dd2 dc supply voltage (i/o) 3.0 to 3.6v t c case temperature range (c) screening: -55 to +125 c (w) screening: -40 to +125 c v in dc input voltage 0v to v dd2
6 dc electrical charac teristics (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019 at 3.0e5 rad(si). 1. measured only for in itial qualification and after process or design ch anges that could affect input/output capacitance. 2. supplied as a design limit bu t not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. v ih = v dd2 (max), v il = 0v. symbol parameter condition min max unit v ih high-level input voltage 0.7*v dd2 v v il low-level input voltage 0.3*v dd2 v v ol low-level output voltage i ol = 8ma,v dd2 =v dd2 (min) 0.2*v dd2 v v oh high-level output voltage i oh = -4ma,v dd2 =v dd2 (min) 0.8*v dd2 v c in 1 input capacitance ? = 1mhz @ 0v 12 pf c io 1 bidirectional i/o capacitance ? = 1mhz @ 0v 12 pf i in input leakage current v in = v dd2 and v ss -2 2 a i oz three-state output leakage current v o = v dd2 and v ss v dd2 = v dd2 (max), g = v dd2 (max) -2 2 a i os 2, 3 short-circuit output current v dd2 = v dd2 (max), v o = v dd2 v dd2 = v dd2 (max), v o = v ss -100 +100 ma i dd1 (op 1 )v dd1 supply current operating @ 1mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 25 ma i dd1 (op 2 )v dd1 supply current operating @ 50mhz, inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 200 ma i dd2 (op 1 )v dd2 supply current operating @ 1mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 1ma i dd2 (op 2 )v dd2 supply current operating @ 50mhz, inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 12 ma i dd1 (sb) 4 i dd2 (sb) 4 supply current standby @ 0hz cmos inputs , i out = 0 e1 = v dd2 -0.2, e2 = gnd v dd1 = v dd1 (max), v dd2 = v dd2 (max) 25 100 ma a i dd1 (sb) 4 i dd2 (sb) 4 supply current standby a(16:0) @ 50mhz cmos inputs , i out = 0 e1 = v dd2 - 0.2, e2 = gnd, v dd1 = v dd1 (max), v dd2 = v dd2 (max) 25 100 ma a
7 ac characteristics read cycle (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019. 1. guaranteed by character ization, but not tested. 2. three-state is defined as a 200mv change from steady-state output voltage. 3. the et (enable true) notation refe rs to the latter falling edge of e1 or rising edge of e2. 4. the ef (enable false) notation refe rs to the latter rising edge of e1 or falling edge of e2. symbol parameter ut8er512 min max unit figure t avav 1 1 read cycle time 20 ns 3a t avqv1 address to data valid from address change 20 ns 3c t axqx 2 output hold time 5 ns 3a t glqx1 1,2 g -controlled output enable time 2 ns 3c t glqv g -controlled output data valid 8 ns 3c t ghqz1 2 g -controlled output three-state time 2 6 ns 3c t etqx 2,3 e-controlled output enable time 5 ns 3b t etqv 3 e-controlled access time 20 ns 3b t efqz 4 e-controlled outpu t three-state time 2 37ns3b t etmv e-controlled error flag time 20 ns 3b t av m v address to error flag valid 20 ns 3a t axmx address to error flag hold time from address change 3 ns 3a t glmv g -controlled error flag valid 7 ns 3c t glmx g -controlled error flag enable time 5 ns 3c t etmx e-controlled error fl ag enable time 5 ns 3b
8 assumptions: 1. e1 and g < v il (max) and e2 and w > v ih (min) 2. busy > v oh (min) 3. reading uninitialized addresses will cause mbe to be asserted. a(18:0) dq(31:0) figure 3a. sram read cycle 1: address access t avav1 t avqv1 , t avmv t axqx , t axmx previous valid data valid data valid data mbe a(18:0) latter of e1 low, and e2 high data valid t efqz t etqv , t etmv t etqx , t etmx dq(31:0) data valid mbe assumptions: 1. g < v il (max) and w > v ih (min) 2. busy > v oh (min) 3. reading uninitialized ad dresses will cause mbe to be asserted. figure 3b. sram read cycl e 2: chip enable access figure 3c. sram read cycl e 3: output enable access a(18:0) mbe g assumptions: 1. e1 < v il (max), e2 and w > v ih (min) 2. busy > v oh (min) 3. reading uninitialized addresses will cause mbe to be asserted. t glmv t glmx t avqv1 data valid dq(31:0) t glqx1 t ghqz1 t glqv data valid
9 ac characteristics write cycle (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes : * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019. 1. tested with g high. 2. three-state is defined as 200mv cha nge from steady-state output voltage. symbol parameter min max unit figure t avav 2 1 write cycle time 10 ns 4a/4b t etwh device enable to end of write 17 ns 4a t av e t address setup time for write (e1 /e2- controlled) 0 ns 4b t av w l address setup time for write (w - controlled) 0 ns 4a t wlwh write pulse width 7 ns 4a t whax address hold time for write (w - controlled) 0 ns 4a t efax address hold time for device enable (e1 /e2- controlled) 0 ns 4b t wlqz 2 w - controlled three-state time 7 ns 4a/4b t whqx 2 w - controlled output enable time 6 ns 4a t etef device enable pulse width (e1/ e2 - controlled) 17 ns 4b t dvwh data setup time 5 ns 4a t whdx data hold time 0 ns 4a t wlef device enable controlled write pulse width 17 ns 4b t dvef data setup time 5 ns 4a/4b t efdx data hold time 0 ns 4b t av w h address valid to end of write 10 ns 4a t whwl 1 write disable time 1 ns 4a t etqz enable q to output tri-state 7 ns 4b
10 assumptions: 1. g < v il (max). (if g > v ih (min) then q(31:0) and mbe will be in three- state for the entire cycle.) 2. busy > v oh (min) w t avwl figure 4a. sram write cycle 1: w - controlled access a(18:0) q(31:0) e1 t avav2 d(31:0) applied data t dvwh, t dvef t whdx t etwh, t wlef t wlwh t whax t whqx t wlqz t avwh t whwl e2
11 t efdx assumptions & notes: 1. g < v il (max). (if g > v ih (min) then q(31:0) and mbe will be in three-stat e for the entire cycle.) 2. either e1 / e2 scenario can occur. 3. busy > v oh (min) a(18:0) figure 4b. sram write cycle 2: enable - controlled access w e1 d(31:0) applied data e1 q(31:0) t etqz t etef t wlef t dvef t avav2 t avet t avet t efax t efax or e2 e2
12 table 4: edac programming configuration table addr bit parameter value function a (0 - 3) scrub rate 1 0-15 as scrub rate changes from 0 - 15, then the interval between scrub cycles will change as follows: 0 = 20 mhz 6 = 312 khz 11 = 9.76 khz 1 = 10 mhz 7 = 156 khz 12 = 4.88 khz 2 = 5 mhz 8 = 78 khz 13 = 2.44 khz 3 = 2.5 mhz 9 = 39 khz 14 = 1.22 khz 4 4 = 1.25 mhz 10 = 19.5 khz 15 = .61 khz 4 5 = 625 khz a (4 - 7) busy to scrub 2 0-15 if busy changes from 0 - 15, then the interval t blsl between scrub and busy will change as follows: 0 = 0 ns 6 = 300 ns 11 = 550 ns 1 = 50 ns 7 = 350 ns 12 = 600 ns 2 = 100 ns 8 = 400 ns 13 = 650 ns 3 = 150 ns 9 = 450 ns 14 = 700 ns 4 = 200 ns 10 = 500 ns 15 = 750 ns 5 = 250 ns a (8) bypass edac bit 3 0, 1 if 0, then normal edac operation will occur. if 1, then edac will be bypassed. a (9) read / write control register 0, 1 0 = a0 to a8 will be written to the control register 1 = control register will be asserted to the data bus notes: 1. default scrub rate is 156khz. 2. the default for t blsl is 500 ns. 3.the default state for a8 is 0. 4. below testing capability. a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 note: 1. see table 4 for control register definitions scrub rate (default = 7h) busy to scrub (default = ah) edac bypass (default = 0h) read / write control register
13 symbol parameter min max unit figure t avav 3 address valid to address valid for control register cycle 100 ns 5a t av c l address valid to control low 200 ns 5a t av e x address valid to enable valid 200 ns 5a t blsl user programmable - busy low to scrub see table 4 5b t slsh1 scrub low to scrub high 200 300 ns 5b t slsh2 scrub low to scrub high 200 ns 5c t shbh scrub high to busy high 50 75 ns 5b t av q v 3 address to data valid control register read 200 ns 5a t glqx3 output control output time 3 ns 5a t ghqz3 output tri-state time 7 ns 5a ac characteristics for edac function (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes: * post-radiation perform ance guaranteed at 25 o c per mil-std-883 method 1019. 1. see table 4 for user programmable information.
14 note: 1. mbe is driven high by the user. 2. lower 9 bits of the last address are used to configure the control register. addr e1 low, and e2 high g t avcl t avav3 mbe figure 5a. control register cycle assumptions: 1. scrub > v oh before the start of the confi guration cycle. ignore scrub during configuration cycle. 70000h 7ff00h 3a500h 55a00h 10500h 00xxxh t avex figure 5b. master mode scrub cycle scrub busy t slsh1 assumptions: 1. the conditions pertain to both a read or write. t blsl t shbh t glqx3 t avqv3 control reg. read control reg read t ghqz3 scrub t slsh2 figure 5c. slave mode scrub cycle assumptions: 1. the conditions pertain to both a read or write.
15 notes: 1. 50pf including scope probe and test socket. 2. measurement of data output occurs at the lo w to high or high to low transition mid-point (i.e., cmos input = v dd2 /2). 90% input pulses 10% < 2ns < 2ns cmos 0.0v v dd2 -0.05v figure 7. ac test loads and input waveforms 1.5v 188 ohms 50pf -55 o c 25 o c 125 o c -40 o c
16 packaging notes: 1. all exposed metallized areas are gold plated over nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance with mil-prf-38535. figure 8. 68-lead ceramic quad flatpack
17 ordering information 512k x 32 sram ut **** ** - * * * * * lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening: (c) = military temperature range flow (-55 c to +125 c) (p) = prototype flow (w) = extended industrial temperature range flow (-40 c to +125 c) package type: (w) = 68-lead ceramic quad flatpack access time: (20) = 20ns read / 10ns write access times (68 cqfp) device type: (8er512k32m) =512k x 32 sram master device (8er512k32s) = 512k x 32 sram slave device notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when or dering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex colorado spri ngs manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per aero flex colorado springs manu facturing flows document. devices are tested at -55 c, notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when or dering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex colorado spri ngs manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per aero flex colorado springs manu facturing flows document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
18 512k x 32 sram: smd 5962 - ******* ** lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (x) = 68-lead ceramic quad flatpack class designator: (q) = qml class q (v) = qml class v device type (01) = 20ns read / 10ns write master device (-55 c to +125 c) (02) = 20ns read / 10ns write master device (-40 c to +125 c) (03) = 20ns read / 10ns write slave device (-55 c to +125 c) (04) = 20ns read / 10ns write slave device (-40 c to +125 c) drawing number: 06261 total dose: (r) = 100k rad(si) (f) = 300k rad(si) federal stock class designator: no options ** * notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
19 notes
20 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colordo springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel

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